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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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#include "../Concepts.hpp"
#include "../GenericID.hpp"
#include "../Helpers.hpp"
#include "../Index.hpp"
#include "../tdv/SinglePassStrategies.hpp"
#include "Grid.hpp"
#include <chrono>
#include <optional>
Go to the source code of this file.
Classes | |
class | stencil::tiling::StencilUpdateKernel< TransFunc, TDVKernelArgument, n_processing_elements, output_tile_width, output_tile_height, in_pipe, out_pipe > |
A kernel that executes a stencil transition function on a tile. More... | |
class | stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy > |
A grid updater that applies an iterative stencil code to a grid. More... | |
struct | stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params |
Parameters for the stencil updater. More... | |
Namespaces | |
namespace | stencil |
namespace | stencil::tiling |