StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params Struct Reference

Parameters for the stencil updater. More...

#include <StencilUpdate.hpp>

Public Attributes

transition_function
 An instance of the transition function type.
 
Cell halo_value = Cell()
 The cell value to present for cells outside of the grid.
 
uindex_t iteration_offset = 0
 The iteration index offset.
 
uindex_t n_iterations = 1
 The number of iterations to compute.
 
sycl::device device = sycl::device()
 The device to use for computations.
 
bool blocking = false
 Should the stencil updater block until completion, or return immediately after all kernels have been submitted.
 
bool profiling = false
 Enable profiling.
 

Detailed Description

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
struct stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params

Parameters for the stencil updater.

Member Data Documentation

◆ blocking

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
bool stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::blocking = false

Should the stencil updater block until completion, or return immediately after all kernels have been submitted.

Choosing one option or the other won't effect the correctness: For example, if you choose a non-blocking stencil updater and immediately try to access the grid after the updater has returned, SYCL/OneAPI will block your thread until the computations are complete and it can actually provide you access to the data.

◆ device

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
sycl::device stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::device = sycl::device()

The device to use for computations.

For some setups, it might be necessary to explicitly select the device to use for computation. This can be done for example with the sycl::ext::intel::fpga_selector_v class in the sycl/ext/intel/fpga_extensions.hpp header. This selector will select the first FPGA it sees.

◆ halo_value

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
Cell stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::halo_value = Cell()

The cell value to present for cells outside of the grid.

◆ iteration_offset

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
uindex_t stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::iteration_offset = 0

The iteration index offset.

This offset will be added to the "actual" iteration index. This way, simulations can "resume" with the next timestep if the intermediate grid has been evaluated by the host.

◆ n_iterations

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
uindex_t stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::n_iterations = 1

The number of iterations to compute.

◆ profiling

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
bool stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::profiling = false

Enable profiling.

Setting this option to true will enable the recording of computation start and end timestamps. The recorded kernel runtime can be fetched using the StencilUpdate::get_kernel_runtime method.

◆ transition_function

template<concepts::TransitionFunction F, uindex_t n_processing_elements = 1, uindex_t tile_width = 1024, uindex_t tile_height = 1024, tdv::single_pass::Strategy< F, n_processing_elements > TDVStrategy = tdv::single_pass::InlineStrategy>
F stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >::Params::transition_function

An instance of the transition function type.

User applications may store runtime parameters here.


The documentation for this struct was generated from the following file: