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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
|
This is the complete list of members for stencil::tdv::single_pass::PrecomputeOnHostStrategy::GlobalState< TransFunc, max_n_iterations >::KernelArgument, including all inherited members.
| KernelArgument(GlobalState &global_state, sycl::handler &cgh, uindex_t i_iteration, uindex_t n_iterations) | stencil::tdv::single_pass::PrecomputeOnHostStrategy::GlobalState< TransFunc, max_n_iterations >::KernelArgument | inline |
1.9.8