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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
|
This is the complete list of members for stencil::tdv::single_pass::PrecomputeOnDeviceStrategy::GlobalState< TransFunc, max_n_iterations >, including all inherited members.
| GlobalState(TransFunc trans_func, uindex_t iteration_offset, uindex_t n_iterations) | stencil::tdv::single_pass::PrecomputeOnDeviceStrategy::GlobalState< TransFunc, max_n_iterations > | inline |
| TDV typedef | stencil::tdv::single_pass::PrecomputeOnDeviceStrategy::GlobalState< TransFunc, max_n_iterations > |
1.9.8