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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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Classes | |
class | stencil::cpu::Grid< Cell > |
A grid class for the CPU backend. More... | |
class | stencil::cpu::Grid< Cell >::GridAccessor< access_mode > |
An accessor for the grid. More... | |
Namespaces | |
namespace | stencil |
namespace | stencil::cpu |