StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy > Member List

This is the complete list of members for stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >, including all inherited members.

get_kernel_runtime() conststencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >inline
get_n_processed_cells() conststencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >inline
get_params()stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >inline
get_walltime() conststencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >inline
GridImpl typedefstencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >
halo_radiusstencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >static
operator()(GridImpl &source_grid)stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >inline
StencilUpdate(Params params)stencil::tiling::StencilUpdate< F, n_processing_elements, tile_width, tile_height, TDVStrategy >inline