StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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stencil::cpu::Grid< Cell > Member List

This is the complete list of members for stencil::cpu::Grid< Cell >, including all inherited members.

copy_from_buffer(sycl::buffer< Cell, 2 > other_buffer)stencil::cpu::Grid< Cell >inline
copy_to_buffer(sycl::buffer< Cell, 2 > other_buffer)stencil::cpu::Grid< Cell >inline
dimensionsstencil::cpu::Grid< Cell >static
get_buffer()stencil::cpu::Grid< Cell >inline
get_grid_height() conststencil::cpu::Grid< Cell >inline
get_grid_width() conststencil::cpu::Grid< Cell >inline
Grid(uindex_t c, uindex_t r)stencil::cpu::Grid< Cell >inline
Grid(sycl::range< 2 > range)stencil::cpu::Grid< Cell >inline
Grid(sycl::buffer< Cell, 2 > other_buffer)stencil::cpu::Grid< Cell >inline
Grid(Grid const &other_grid)stencil::cpu::Grid< Cell >inline
make_similar() conststencil::cpu::Grid< Cell >inline
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