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StencilStream v3.0.0
SYCL-based Stencil Simulation Framework Targeting FPGAs
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#include "GenericID.hpp"
#include "Helpers.hpp"
#include "Index.hpp"
#include <bit>
#include <sycl/ext/intel/ac_types/ac_int.hpp>
#include <variant>
Go to the source code of this file.
Classes | |
class | stencil::Stencil< Cell, stencil_radius, TimeDependentValue > |
The stencil buffer. More... | |
Namespaces | |
namespace | stencil |